It is well known in the art to form split-gate memory cells as an array of such cells, where the memory cells are formed in pairs, where each pair of memory cells shares a common erase gate and a common source region. For example, U.S. Pat. No. 7,868,375 (which is incorporated herein by reference for all purposes) discloses such a memory array.
FIG. 1 illustrates a conventional pair of split-gate memory cells 1. Each memory cell 1 includes a source region (source line) 2 and a drain region (bit line) 3, with a channel region 4 defined in the substrate there between. A floating gate 5 is disposed over and insulated from a first portion of the channel region 4, and a word line gate 6 is disposed over and insulated from a second portion of the channel region 4. A coupling gate 7 is formed over and insulated from the floating gate 5. An erase gate 8 is formed over and insulated from the source region 2.
The floating gate 5 for each cell is programmed by injecting electrons from a stream of electrons travelling along the channel region 4 up onto the floating gate 5 (via hot electron injection). This is illustrated in FIG. 1 by the electron arrow traveling along the channel region 4, and then up through the insulation material to the floating gate 5. The floating gate 5 is erased by inducing tunneling of electrons from the floating gate 5 to the erase gate 8 (through Fowler Nordheim tunneling). This is illustrated in FIG. 1 by the electron arrow traveling from the floating gate 5, through the insulation, to the erase gate 8. One non-limiting example of the erase, read and program voltages is illustrated in FIG. 2, where the selected (Sel.) lines are those containing the memory cell being operated on and the unselected (Unsel.) lines are those not containing the memory cell being operated on. Each memory cell is individually read by placing a positive voltage on that cell's word line gate to turn on the channel region portion below, and measuring the conductivity of its channel region (which is affected by whether or not the cell's floating gate is programmed with electrons which dictates whether the underlying channel region portion is conductive). Each memory cell is individually programmed by streaming electrons along its channel region and coupling a high positive voltage to its floating gate.
Given the number of gates in this cell design, it is challenging to scale down the memory cells in size.